1. Field of the Invention
The present invention relates to a multiple chamber wafer processing tool and, more particularly, to a method and apparatus for automatically generating a schedule(s) for a semiconductor wafer within a multiple chamber semiconductor wafer processing tool.
2. Description of the Background Art
Semiconductor wafers are processed to produce integrated circuits using a plurality of sequential process steps. These steps are performed using a plurality of process chambers. An assemblage of process chambers served by a wafer transport robot is known as a multiple chamber semiconductor wafer processing tool or cluster tool. Examples of cluster tools include the Centura(copyright) HDP CVD System and the Endura(copyright) system manufactured by Applied Materials, Inc. of Santa Clara, Calif. FIG. 1 depicts, in part, a schematic diagram of the Endura(copyright) System.
The cluster tool 100 contains, for example, four process chambers 104, 106, 108, 110, a transfer chamber 112, a preclean chamber 114, a buffer chamber 116, a wafer orienter/degas chamber 118, a cooldown chamber 102, and a pair of loadlock chambers 120 and 122. Each chamber represents a different stage or phase of semiconductor wafer processing. The buffer chamber 116 is centrally located with respect to the loadlock chambers 120 and 122, the wafer orienter/degas chamber 118, the preclean chamber 114 and the cooldown chamber 102. To effectuate wafer transfer amongst these chambers, the buffer chamber 116 contains a first robotic transfer mechanism 124. The wafers 128 are typically carried from storage to the system in a plastic transport cassette 126 that is placed within one of the loadlock chambers 120 or 122. The robotic transport mechanism 124 transports the wafers 128, one at a time, from the cassette 126 to any of the three chambers 118, 102, or 114. Typically, a given wafer is first placed in the wafer orienter/degas chamber 118, then moved to the preclean chamber 114. The cooldown chamber 102 is generally not used until after the wafer is processed within the process chambers 104, 106, 108, 110. Individual wafers are carried upon a wafer transport blade 130 that is located at the distal end of the first robotic mechanism 124. The transport operation is controlled by a sequencer 136.
The transfer chamber 112 is surrounded by and has access to the four process chambers 104, 106, 108 and 110 as well as the preclean chamber 114 and the cooldown chamber 102. To effectuate transport of a wafer amongst the chambers, the transfer chamber 112 contains a second robotic transport mechanism 132. The mechanism 132 has a wafer transport blade 134 attached to its distal end for carrying the individual wafers. In operation, the wafer transport blade 134 of the second transport mechanism 132 retrieves a wafer from the preclean chamber 114 and carries that wafer to the first stage of processing, for example, a physical vapor deposition (PVD) stage within chamber 104. Once the wafer is processed and the PVD stage deposits material upon the wafer, the wafer can then be moved to a second stage of processing and so on.
Once processing is complete within the process chambers, the transport mechanism 132 moves the wafer from the process chamber and transports the wafer to the cooldown chamber 102. The wafer is then removed from the cooldown chamber using the first transport mechanism 124 within the buffer chamber 116. Lastly, the wafer is placed in the transport cassette 126 within the loadlock chamber 122.
A cluster tool may be coupled to a factory interface comprising at least one factory interface robot, one or more metrology chambers/defect control chambers and one or more load ports, and one or more wafer orienting chambers. The factory interface is coupled to the load locks of the cluster tool.
More generally, a cluster tool contains n chambers, denoted by C1, C2, . . . , Cn, one or more transfer chambers (robots) 112 and 116, and one or more loadlocks 120 and 122. The exact arrangement of chambers, robots and loadlocks is referred to as the xe2x80x9cconfigurationxe2x80x9d of the tool. A wafer Wa to be processed is taken from a loadlock, placed successively into various chambers as each chamber performs a particular process upon the wafer.
A wafer""s trace is the trajectory of a particular wafer through the cluster tool; that is, a trace is the order in which chambers are visited by a wafer (not necessarily Ci+1 after Ci). This should be distinguished from the term xe2x80x9cprocessing sequencexe2x80x9d which is the order of applying processes (recipes) to a wafer. If more than one chamber performs the same process (parallel chambers), a given processing sequence may be satisfied by several different traces.
A wafer which completes its processing sequence and is returned to the loadlock is said to be processed by the tool. Roughly speaking, a tool""s throughput is the number of wafers processed by the tool per unit of time. That is, if the tool needs t seconds to process nt wafers, then                               S          t                :=                              n            t                    t                                    (        3        )            
is the tool""s throughput measured in the interval [0,t].
There are many ways to improve the tool""s throughput for a given processing sequence. However, one important improvement is to use efficient scheduling routines for a given processing sequence.
The optimization of scheduling involves the choice of criteria used in deciding when to transfer a wafer from one chamber into the next (and which wafers should be moved, if any, prior to that move). A routine which schedules the movement of wafers through the cluster tool (based on a given processing sequence) is referred to as a xe2x80x9cscheduling routine.xe2x80x9d
The steady-state throughput of a tool under scheduling routine A is denoted by S(A). If n greater than 1 then, depending on a given processing sequence, one may consider a number of scheduling routines that fulfill the processing sequence. The routine which maximizes the value of throughput is deemed the xe2x80x9coptimumxe2x80x9d routine and the maximum attainable value of throughput is known as the tool""s xe2x80x9ccapacity.xe2x80x9d That is, if A is the set of all possible scheduling routines for a given processing sequence, then A* is optimum if
S(A*)=max{S(A)|A∈A}xe2x80x83xe2x80x83(4)
Clearly, the tool""s capacity S(A*) depends on a given processing sequence as well as on chamber and robot parameters within the processing sequence. The problem of finding efficient scheduling routines for a given processing sequence (especially, finding optimum routines, where possible) is of considerable practical importance.
Presently there is not an automatic method of determining the best schedule, given a particular trace, that provides the highest throughput for that trace. Typically, a trial and error method is used until a schedule is determined that provides a sufficient throughput. However, the sufficient throughput may not be the best throughput that is possible for a given trace.
Therefore, a need exists in the art for a method and apparatus that determines all possible schedules given a particular trace and, using a throughput modeling program determines the throughput for each of the possible schedules and selects a schedule for use within a cluster tool that provides the maximum throughput for the given trace.
The disadvantages heretofore associated with the prior art are overcome by an invention of a method and apparatus for determining all possible schedules that accomplish a given trace, applying a throughput model to each of the schedules, and determining the schedule or schedules that result in the highest throughput.
More specifically, a first embodiment of the invention uses a set of deterministic rules to compute the various schedules. First, a schedule is defined as a series of xe2x80x9clettersxe2x80x9d that form a xe2x80x9cwordxe2x80x9d. Each letter in the word defines a possible positioning of wafers within a cluster tool. Of course, the positioning of the wafers within the tool must fulfill the trace, i.e., each letter must follow from a predecessor letter in accordance with a particular set of rules that define the trace.
Given a letter (input letter) representing present wafer positions, the invention computes all possible successor wafer positions, i.e., all possible valid successor letters, as well as the total number of successors for the input letter. The invention provides individual xe2x80x9cmodulesxe2x80x9d for successor computation for serial traces, parallel traces, and mixed traces. Using a backtracking technique to repeatedly compute, from any letter, all possible successor letters, and then compute all possible successor letters of the successor letters, a schedule tree is derived. The schedule tree contains all possible schedules that will fulfill a given trace. Each and every schedule can then be modeled to determine the expected throughput of each schedule. By comparing the throughput associated with each schedule, an optimal schedule or schedules is identified.
In a second embodiment of the invention, a method and apparatus performs successive application of three digraph based processes. First, a digraph GN({0,1}N,E) is formed to determine a directed edge from vertex {overscore (u)}∈{0,1}N to vertex {overscore (u)}∈{0,1}N only if {overscore (u)} and {overscore (v)} differ in at most two coordinates and {overscore (v)} is chosen by modifying {overscore (u)} according to the rules derived from a cluster tool""s operation. N is the number of chambers in the tool, E is an edge set, u and v are coordinates representing wafer positions in the tool. Second, the invention determines simple cycles in GN({0,1}N,E) that correspond to various schedules for moving wafers through the system. Third, by using a throughput simulation program all possible cycles (schedules) are executed and the schedule that yields the highest throughput is chosen as an optimal schedule.